Mon 15 Jun 2015 16:25 - 16:50 at PLDI Main RED (Portland 256) - Optimization Chair(s): Michelle Strout

In a network-on-chip (NoC) based multicore architecture, an off-chip data access (main memory access) needs to travel through the on-chip network, spending considerable amount of time within the chip (in addition to the memory access latency). In addition, it contends with on-chip (cache) accesses as both use the same NoC resources. In this paper, focusing on multithreaded applications, we propose a compiler-based off-chip data access localization strategy, which places data elements in the memory space such that an off-chip access traverses a minimum number of links (hops) to reach the memory controller that handles this access request. We present an extensive experimental evaluation of our optimization strategy using a set of 13 multithreaded application programs under both private and shared last level caches. The results collected emphasize the importance of optimizing the off-chip data accesses.

Mon 15 Jun
Times are displayed in time zone: Tijuana, Baja California change

16:00 - 17:15
OptimizationResearch Papers at PLDI Main RED (Portland 256)
Chair(s): Michelle StroutColorado State University
16:00
25m
Talk
LaminarIR: Compile-Time Queues for Structured Streams
Research Papers
Yousun KoYonsei University, Bernd BurgstallerYonsei University, Bernhard ScholzThe University of Sydney
Media Attached
16:25
25m
Talk
Optimizing Off-Chip Accesses in Multicores
Research Papers
Wei DingPennsylvania State University, Xulong TangPenn State, Mahmut Taylan KandemirPennsylvania State University, Yuanrui ZhangIntel, Emre KultursayPennsylvania State University
Media Attached
16:50
25m
Talk
Improving Compiler Scalability: Optimizing Large Programs at Small Price
Research Papers
Sanyam MehtaUniversity of Minnesota, Pen-Chung YewUniversity of Minnesota
Media Attached