Sat 13 Jun 2015 16:00 - 16:30 at C122 - Paper Session 4 Chair(s): David Grove

Image processing pipelines are continuously being developed to deduce more information about objects captured in images. To facilitate the development of such pipelines several Domain Specific Languages (DSLs) have been developed that provide constructs for easy specification of such computations. It is then upto the DSL compiler to generate code to efficiently execute the pipeline on multiple hardware architectures. While such compilers are getting ever more sophisticated, to achieve large scale adoption these DSLs have to beat or at least match the performance that can be achieved by a skilled programmer.

Many of these pipelines use a sequence of convolution kernels that are memory bandwidth bound. One way to address this bottleneck is through use of tiling. In this paper we describe an approach to tiling within the context of a DSL called Forma. Using the high-level specification of the pipeline in this DSL, we describe a code generation algorithm that fuses multiple stages of the pipeline through the use of tiling to reduce the memory bandwidth requirements on both GPU and CPU. Using this technique improves the performance of pipelines like Canny Edge Detection by 58% on NVIDIA GPUs, and of the Harris Corner Detection pipeline by 71%.

Sat 13 Jun

16:00 - 18:00: ARRAY - Paper Session 4 at C122
Chair(s): David GroveIBM Research
ARRAY-2015-papers16:00 - 16:30
ARRAY-2015-papers16:30 - 17:00
ARRAY-2015-papers17:00 - 17:30
ARRAY-2015-papers17:30 - 18:00